In interline transfer type imaging devices, photogenerated charge is colllected on a pixel or photoreceptor element such as a pn junction (photodiode) or under the gate of the photocapacitor, for a period of time and then transferred into a charge coupled register to be detected by an output circuit. In an area array of such pixels it is necessary to transfer the collected photocharge, first into a vertical shift register and then to a horizontal shift register, finally, reaching a charge sensitive detector or amplifier. Prior art interline transfer type devices have largely been arranged to be read out in what has been termed the interlaced mode of operation. In a typical prior art device shown schematically in FIGS. 1 and 2, alternate rows of photoreceptors are read out in sequence, odd numbered rows being associated with one, so called, field, and even numbered rows associated with a second field. FIG. 2 is a schematic vertical section taken along the line A--A of FIG 1. Referring now to FIGS. 1 and 2, a given field of pixels, rows 1, 3, 5, etc., is addressed by application of a voltage to electrodes 20 and 30 which are both conneted to the same vertical clock line, .phi..sub.1. Upon application of this voltage, photocharge is transferred, as indicated schematically by the horizontal arrows in FIG. 1 to the buried channel 40 of the vertical shift register (see FIG. 2). This vertical shift register is composed of buried channel 40, electrodes 20 and 30 which are connected to vertical clock line .phi..sub.1, and electrodes 50 and 60 are connected to vertical clock line .phi..sub.2. These electrodes are separated from the substrate semiconductor 70 by an insulating layer 80. The regions 65 beneath electrodes 30 and 60 are ion implanted to provide a potential energy difference between regions 25 and 26, controlled by voltages on the .phi..sub.1 clock line, and between regions 55 and 56, controlled by voltages on the .phi..sub.2 clock line. To read-out image information on, say, odd numbered rows of pixels, line .phi..sub.1 is pulsed in a manner to effect transfer of the photocharge from the photodiodes to the buried channel region under electrode 20. This odd-field transfer pulse is indicated in FIG. 3a. The photocharge is then transferred via the vertical and horizontal CCD shift registers to a charge detection amplifier. Subsequently, sites on even numbered rows are read out as a second field in a similar manner by application of an even-field transfer pulse, indicated schematically in FIG. 3a, thus transferring photocharge from even numbered rows of pixels to the buried channel region beneath electrodes 50. Subsequent clocking transfers the photocharge to the output amplifier via the vertical and horizontal shift registers. The vertical clocking voltages for this interlaced type of operation are indicated schematically in FIG. 3a. However, with such a prior art device architecture it is not possible to read-out each row of pixels sequentially, i.e., in what would be called a non-interlaced mode, since only one half of a vertical shift register cell is provided for each row of pixels. For a non-interlaced read-out to be achieved a complete vertical CCD shift register cell is required for each row of photodiodes since photocharge from all pixels must be transferred into the vertical shift register simultaneously and maintained as separate charge packets throughout transfer to the output amplifier. In order to provide for such a non-interlaced read-out sequence using such prior art, each pixel would need to contain at least four separate CCD electrodes if a similar manufacturing process is to be used and the same number of clocking voltages maintained. Alternatively, if three levels of overlapping electrodes are employed with a three-phase clocking sequence, such as disclosed by Tsaur et al in IEEE Electron Device Letters, 10, 361-363, 1989, a non-interlaced read-out may be achieved but at the expense of additional process and system complexity and a sacrifice of available photosensitive area but without the option of achieving an interlaced readout with the same device.
In U.S. Pat. No. 4,330,796, Anognostopoulos et al disclose a non-interlaced interline transfer type CCD image sensor which employs three electrodes per pixel and a "meander channel" CCD which occupies a large fraction of the total pixel area. However, as discussed in Loose et al, U.S. Pat. No. 4,613,402, if the barrier region implants in the meander channel CCD are not precisely aligned, parasitic potential wells or barriers will be present in the CCD, thus leading to transfer inefficiency and poor performance. Furthermore, the device of Anognostopoulos et al does not allow selection of either interlaced or non-interlaced read-out.